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| MC10E212, MC100E212 5V ECL 3-Bit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed with control logic which greatly facilitates its use in boundary scan applications. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS 1 28 * * * * * * Scannable Version E112 Driver 1025 ps Max. CLK to Output Dual Differential Outputs Master Reset PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V Internal Input Pulldown Resistors PLCC-28 FN SUFFIX CASE 776 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week MC10E212FN AWLYYWW 1 28 * * ESD Protection: > 1 KV HBM, > 75 V MM * Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test * Moisture Sensitivity Level 1 * Flammability Rating: UL-94 code V-0 @ 1/8", * Oxygen Index 28 to 34 Transistor Count = 259 devices MC100E212FN AWLYYWW For Additional Information, see Application Note AND8003/D ORDERING INFORMATION Device MC10E212FN MC10E212FNR2 MC100E212FN MC100E212FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping 37 Units/Rail 500 Units/Reel 37 Units/Rail 500 Units/Reel (c) Semiconductor Components Industries, LLC, 2006 June, 2006 - Rev. 5 1 Publication Order Number: MC10E212/D MC10E212, MC100E212 5 LOGIC DIAGRAM AND PINOUT ASSIGNMENT SHIFT MR NC S-OUT VCCO Q2b Q2a LOAD CLK D2 VEE D1 D0 S-IN 26 27 28 1 LOGIC DIAGRAM 1 1 0 D S-OUT Q2b Q2a Q2a Q2b 25 24 23 22 21 20 19 18 17 16 Q2b Q2a VCC Q1b Q1a Q1b Q1a D2 0 Q 2 3 4 5 Pinout: 28-Lead PLCC (Top View) 15 14 13 12 1 D1 0 1 0 D Q Q1b Q1a Q1a Q1b 6 7 8 9 10 11 1 D0 S-IN LOAD SHIFT CLK MR 0 1 0 D Q Q0b Q0a Q0a Q0b NC VCCO Q0a Q0b Q0a Q0b VCCO * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. PIN DESCRIPTION PIN D0 - D2 S-IN LOAD SHIFT CLK MR S-OUT Q[0:2]a, Q[0:2]b Q[0:2]a, Q[0:2]b VCC, VCCO VEE NC FUNCTION ECL Data Inputs ECL Scan Input ECL LOAD/HOLD Control ECL Scan Control ECL Clock ECL Reset ECL Scan Output ECL True Outputs ECL Inverting Outputs Positive Supply Negative Supply No Connect FUNCTION TABLE LOAD L H X X SHIFT L L H X MR L L L H MODE Load Hold Shift Reset http://onsemi.com 2 MC10E212, MC100E212 MAXIMUM RATINGS (Note 1) Symbol VCC VEE VI Iout TA Tstg JA JC VEE Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) PECL Operating Range NECL Operating Range Wave Solder <2 to 3 sec @ 248C 1. Maximum Ratings are those values beyond which device damage may occur. 0 LFPM 500 LFPM std bd 28 PLCC 28 PLCC 28 PLCC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 -8 6 -6 50 100 0 to +85 -65 to +150 63.5 43.5 22 to 26 4.2 to 5.7 -5.7 to -4.2 265 Units V V V V mA mA C C C/W C/W C/W V V C 10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1) 0C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 0.3 3980 3050 3830 3050 Min Typ 80 4070 3210 3995 3285 Max 96 4160 3370 4160 3520 150 0.5 0.25 4020 3050 3870 3050 Min 25C Typ 80 4105 3210 4030 3285 Max 96 4190 3370 4190 3520 150 0.3 0.2 4090 3050 3940 3050 Min 85C Typ 80 4185 3227 4110 3302 Max 96 4280 3405 4280 3555 150 Unit mA mV mV mV mV A A NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / -0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC-2 volts. 10E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= -5.0 V (Note 1) 0C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 0.3 -1020 -1950 -1170 -1950 Min Typ 80 -930 -1790 -1005 -1715 Max 96 -840 -1630 -840 -1480 150 0.5 0.065 -980 -1950 -1130 -1950 Min 25C Typ 80 -895 -1790 -970 -1715 Max 96 -810 -1630 -810 -1480 150 0.3 0.2 -910 -1950 -1060 -1950 Min 85C Typ 80 -815 -1773 -890 -1698 Max 96 -720 -1595 -720 -1445 150 Unit mA mV mV mV mV A A NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / -0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC-2 volts. http://onsemi.com 3 MC10E212, MC100E212 100E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1) 0C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 0.3 3975 3190 3835 3190 Min Typ 80 4050 3295 4050 3300 Max 96 4120 3380 4120 3525 150 0.5 0.25 3975 3190 3835 3190 Min 25C Typ 80 4050 3255 4120 3525 Max 96 4120 3380 4120 3525 150 0.5 0.2 3975 3190 3835 3190 Min 85C Typ 92 4050 3260 4120 3525 Max 110 4120 3380 4120 3525 150 Unit mA mV mV mV mV A A NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.4 6V / -0.8 V. 2. Outputs are terminated through a 50 ohm resistor to VCC-2 volts. 100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= -5.0 V (Note 1) 0C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 0.3 -1025 -1810 -1165 -1810 Min Typ 80 -950 -1705 -950 -1700 Max 96 -880 -1620 -880 -1475 150 0.5 0.25 -1025 -1810 -1165 -1810 Min 25C Typ 80 -950 -1745 -880 -1475 Max 96 -880 -1620 -880 -1475 150 0.5 0.2 -1025 -1810 -1165 -1810 Min 85C Typ 92 -950 -1740 -880 -1475 Max 110 -880 -1620 -880 -1475 150 Unit mA mV mV mV mV A A NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / -0.8 V. 2. Outputs are terminated through a 50 ohm resistor to VCC-2 volts. AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= -5.0 V (Note 1) 0C Symbol fMAX tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay to Output CLK MR CLK to S-OUT Setup Time D SHIFT LOAD S-IN th Hold Time D SHIFT LOAD S-IN tRR tSKEW tSKEW tJITTER tr tf Reset Recovery Within-Device Skew (Note 1.) Within-Gate Skew (Note 2.) Cycle-to-Cycle Jitter Rise/Fall Times (20 - 80%) 275 250 300 225 300 600 25 100 0 100 350 100 50 TBD 425 650 275 250 300 225 300 600 25 100 0 100 350 100 50 TBD 425 650 275 250 300 225 300 600 25 100 0 100 350 100 50 TBD 425 650 ps ps ps ps ps 175 150 225 150 25 - 50 50 - 50 175 150 225 150 25 - 50 50 - 50 175 150 225 150 25 - 50 50 - 50 ps 575 575 575 800 800 800 1025 1025 1025 575 575 575 800 800 800 1025 1025 1025 575 575 575 800 800 800 1025 1025 1025 ps Min Typ TBD Max Min 25C Typ TBD Max Min 85C Typ TBD Max Unit GHz ps ts 1. 10 Series: VEE can vary +0.46 V / -0.06 V. 100 Series: VEE can vary +0.46 V / -0.8 V. 1. Within-device skew is defined as identical transitions on similar paths through a device. http://onsemi.com 4 MC10E212, MC100E212 2. Within-gate skew is defined as the difference in delays between various outputs of a gate when driven from the same input. Q Driver Device Q 50 W 50 W D Receiver Device D V TT VTT = VCC - 2.0 V Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 - ECLinPS Circuit Performance at Non-Standard VIH Levels AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020 - - - - - - - - - - - ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes Termination of ECL Logic Devices http://onsemi.com 5 MC10E212, MC100E212 PACKAGE DIMENSIONS PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E B U 0.007 (0.180) M T L -M M S N S S -N- Y BRK D 0.007 (0.180) T L -M N S -L- -M- Z W V D X VIEW D-D G1 0.010 (0.250) S T L -M S N S 28 1 A 0.007 (0.180) M M T L -M T L -M S S N N S S Z H 0.007 (0.180) M T L -M S N S R 0.007 (0.180) C G G1 0.010 (0.250) E 0.004 (0.100) K1 J -T- SEATING PLANE K F VIEW S 0.007 (0.180) VIEW S M T L -M S N S S T L -M S N S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.410 0.430 0.040 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.79 2.29 0.33 0.48 1.27 BSC 0.81 0.66 0.51 0.64 11.58 11.43 11.58 11.43 1.07 1.21 1.07 1.21 1.42 1.07 0.50 2 10 10.42 10.92 1.02 http://onsemi.com 6 MC10E212, MC100E212 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 7 MC10E212/D |
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